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71M6545/71M6545H Data Sheet
Table 60 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile
bits have a darker gray background.
Table 60: I/O RAM Map – Functional Order
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CE and ADC
MUX5 2100
MUX_DIV[3:0]
MUX10_SEL[3:0]
MUX4
MUX3
MUX2
MUX1
MUX0
2101
2102
2103
2104
2105
MUX9_SEL[3:0]
MUX7_SEL[3:0]
MUX5_SEL[3:0]
MUX3_SEL[3:0]
MUX1_SEL[3:0]
MUX8_SEL[3:0]
MUX6_SEL[3:0]
MUX4_SEL[3:0]
MUX2_SEL[3:0]
MUX0_SEL[3:0]
CE6
2106
EQU[2:0]
U
CHOP_E[1:0]
RTM_E
CE_E
CE5
CE4
2107
2108
U
SUM_SAMPS[7:0]
SUM_SAMPS[12:8]
CE3
CE2
CE1
2109
210A
210B
U
U
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
CE0
RTM0
210C
210D
DIFF6_E
U
DIFF4_E
U
DIFF2_E
U
DIFF0_E
U
RFLY_DIS
U
U
FIR_LEN[1:0]
PLS_INV
RTM0[9:8]
RTM0
RTM1
RTM2
RTM3
210E
210F
2110
2111
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
CLOCK GENERATION
CKGN 2200
U
U
ADC_DIV
PLL_FAST
RESET
MPU_DIV[2:0]
VREF TRIM FUSES
TRIMT 2309
TRIMT[7:0]
DIO
DIO16
…
DIO32
…
DIO38
…
DIO42
2420
…
243D
…
2443
…
2447
U
U
U
U
U
U
U
U
U
U
U
U
U
U
DIO16[5:0]
…
DIO45[5:0]
…
DIO51[5:0]
…
DIO55[5:0]
84
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